1. Field of the Invention
The present invention relates to a latch circuit for temporarily storing data, a flip-flop circuit including a master latch and a slave latch, a shift register circuit, a serial-parallel converting circuit and a parallel-serial converting circuit formed of flip-flop circuits.
2. Description of the Background Art
FIG. 12 is a circuit diagram showing the structure of a conventional flip-flop circuit. In FIG. 12, CR40 is a clock buffer for converting the level of an input clock T, CR41 is a master latch for holding the logic value of an input signal D and outputting a signal D1 corresponding to the held logic value according to a clock T' outputted from the clock buffer CR40, and CR42 is a slave latch for holding the logic value of the signal D1 outputted from the master latch CR41 and outputting a signal D2 corresponding to the held logic value according to the clock outputted from the clock buffer CR40.
For example, suppose that the flip-flop circuit is formed of bipolar transistors with a base-emitter forward voltage VBE of 0.9 V and a first power-supply voltage VCC of 0 V and a second power-supply voltage VEE of -5.2 V are provided to the flip-flop circuit. The input signal D and the clock T swing between -0.9 V and -1.5 V. In this case, for example, the clock buffer CR40 lowers the center voltage level of the amplitude of the clock to output the clock T' swinging between voltage level of the amplitude of the clock to output the clock T' swinging between -1.8 V and -2.4 V. The master latch CR41 receives the input signal D and the clock T' to output the signal D1 having the same amplitude with the same center voltage level as the input signal D. The slave latch CR42 receives the input signal D1 and the clock T' to output the signal D2 having the same amplitude with the same center voltage level as the input signal D.
Next, circuit structures and operations of the parts of the flip-flop circuit shown in FIG. 12 will be described. A first reference voltage VBB1 and a second reference voltage VBB2 applied to the master latch CR41 and the slave latch CR42 are assumed to be -1.3 V and -2.2 V, respectively. The clock buffer CR40 is formed of an NPN bipolar transistor Q14 having a base receiving the clock T, a collector connected to the first power-supply voltage VCC and an emitter for outputting the clock T' having a converted voltage level, and a resistor R11 having one end connected to the emitter of the transistor Q14 and another end provided with the second power-supply voltage VEE. When the clock T swinging between -0.9 V and -1.5 V is inputted to the base of the transistor Q14, the clock T' swinging between -1.8 V and -2.4 V is outputted at the emitter of the transistor Q14.
The master latch CR41 is formed of resistors R1-R5 and transistors Q1-Q9. The resistor R1 has one end and another end, to the one end of which the first power-supply voltage VCC is applied. The NPN bipolar transistor Q1 has an emitter, a base provided with the input signal D, and a collector connected to another end of the resistor R1. The resistor R2 has one end and another end, to the one end of which the first power-supply voltage VCC is applied. The NPN bipolar transistor Q2 has a collector connected to another end of the resistor R2, a base provided with the first reference voltage VBB1, and an emitter connected to the emitter of the transistor Q1. The NPN bipolar transistor Q3 has an emitter, a collector connected to the emitter of the transistor Q1, and a base provided with the second reference voltage VBB2.
The NPN bipolar transistor Q4 has a base, an emitter, and a collector, the collector of which is connected to another end of the resistor R1. The NPN bipolar transistor Q5 has a base, a collector connected to another end of the resistor R2, and an emitter connected to the emitter of the transistor Q4. The NPN bipolar transistor Q6 has a collector connected to the emitters of the transistors Q4, Q5, a base connected to the emitter of the transistor Q14, and an emitter connected to the emitter of the transistor Q3. A constant-current source I1 has one end connected to the emitters of the transistors Q3 and Q6 and another end supplied with the second power-supply voltage VEE, which outputs a certain current. The NPN bipolar transistor Q8 has a base connected to another end of the resistor R1, a collector to which the first power-supply voltage VCC is applied, and an emitter connected to the base of the transistor Q5. The NPN bipolar transistor Q9 has its collector connected to the first power-supply voltage VCC, its base connected to another end of the resistor R2, and its emitter connected to the base of the transistor Q4. The resistors R4 and R5 each has one end connected to the emitter of the transistor Q8 or Q9 and another end provided with the second power-supply voltage VEE.
The constant-current source I1 is formed of the NPN bipolar transistor Q7 having an emitter, a collector corresponding to the one end of the constant-current source I1, and a base supplied with a voltage VCS always having a certain potential difference with respect to the second power-supply voltage VEE, and the resistor R3 having one end connected to the emitter of the transistor Q7 and another end corresponding to another end of the constant-current source I1.
It is set so that a signal swinging between 0 V and -0.6 V is generated at the collector of the transistor Q1 when the input signal D inputted to the base of the transistor Q1 swings between -0.9 V and -1.5 V, for example. That is to say, if the voltage at the base of the transistor Q1 goes -0.9 V when the transistor Q3 is in an on state, the transistor Q1 turns on and the voltage at another end of the resistor R1 goes -0.6 V. When the voltage at the base of the transistor Q1 goes -1.5 V, the transistor Q1 turns off and another end of the resistor R1 goes 0 V. Since the transistor Q1 and the transistor Q2 turn on/off complementarily to each other, 0 V is generated at another end of the resistor R2 when the transistor Q1 is on and -0.6 V is generated when the transistor Q1 turns off.
The signal D1 swinging between -0.9 V and -1.5 V is generated at the emitters of the transistors Q8 and Q9 according to the signals appearing at the collectors of the transistors Q1 and Q2. When the clock outputted from the clock buffer CR40 causes the transistor Q6 to be on, one of the transistors Q4 and Q5 is always on, since they receive the signal D1 at their respective bases. Then the voltage at the emitters of the transistors Q4 and Q5, or the collector of the transistor Q6, is -1.8 V. When the clock outputted from the clock buffer CR40 causes the transistor Q6 to be off, both of the transistors Q4 and Q5 are in non-operating state, with no current flowing therethrough. These transistors Q1-Q6 operate in the non-saturation region.
In the slave latch CR42, the transistors Q1'-Q7', Q10 and Q11 corresponding to the transistors Q1-Q9 in the master latch CR41 are connected in the same way as the corresponding transistors in the master latch CR41.
Furthermore, an output circuit CR43 for outputting output signals Q, QC of the flip-flop circuit is provided in the stage following the slave latch CR42. The output circuit CR43 is formed of transistors Q12, Q13 having emitters, collectors to which the power-supply voltage VCC is applied, and bases respectively connected to the collectors of the transistors Q1' and Q2', and resistors R9 and R10 each having one end connected to the emitter of the transistor Q12 or Q13, and another end to which the power-supply voltage VEE is applied. The transistors Q12 and Q13 are emitter followers.
When provided with the signal D1 swinging between -0.9 and -1.5 V, the slave latch CR42 operates in the same way as the master latch CR41 to output a signal D2 (Q) which swings between -0.9 and -1.5 V from the output circuit CR43.
When the difference between the first and second power-supply voltages VCC and VEE for operation of the flip-flop circuit becomes as low as 3.3 V, for example, the conventional flip-flop circuit constructed as described above can not stably operate, whatever values are set for the first and second reference voltages VBB1, VBB2 and the voltage VCS1. This is due to the fact that the transistors Q8, Q5, Q6, Q7 are connected in series, and the transistors Q9, Q4, Q6, Q7 are connected in series.
Hence, as shown in FIG. 13, the transistors Q8, Q9 are removed from the master latch CR41 of FIG. 12 to form a master latch CR51, and the transistors Q10, Q11 are removed from the slave latch CR42 of FIG. 12 to form a slave latch CR52. Furthermore, in the master latch CR51 and the slave latch CR52, the bases of the transistors Q4 and Q5 are connected respectively to another ends of the resistors R2 and R1, and the bases of the transistors Q4' and Q5' are connected respectively to the resistors R2' and R1', so as to reduce, by one, the number of the transistors connected in series between the power-supply voltages VCC and VEE. This enables it to operate even if the difference between the power-supply voltages VCC and VEE is 3.3 V. The output circuit CR53 provided in the stage following the slave latch CR52 has the constant-current sources I3 and I4 in place of the resistors R9 and R10 in the output circuit CR43 of FIG. 12, but it operates in the same way. The flip-flop circuit of FIG. 13 has an input level converting circuit CR50 for converting the level of the input signal D. The input level converting circuit CR50 is formed of resistors R15, R16 each having one end provided with the power-supply voltage VCC and another end, an NPN bipolar transistor Q16 having an emitter, a base supplied with the input signal D, and a collector connected to another end of the resistor R15, an NPN bipolar transistor Q17 having an emitter connected to the emitter of the transistor Q16, a base to which the reference voltage VBB3 is applied, and a collector connected to another end of the resistor R16, and a constant-current source I2 connected between the emitters of the transistors Q16, Q17 and the power-supply potential point to which the power-supply voltage VEE is applied.
When the flip-flop circuit is structured as shown in FIG. 13, however, it is necessary to set the amplitude center of the input signal D at -0.95 V, convert the center to -0.15 V in the input level converting circuit CR50, and limit the amplitude of the signals handled by the master latch CR51 and the slave latch CR52 between 0 V and -0.3 V, and it is also necessary to set the center of the amplitude of the output signal at -0.95 V, and limit its amplitude between -0.8 V and -1.1 V.
Since the amplitude of the output signal of the flip-flop circuit is limited to 0.3 V, the signal outputted from the flip-flop circuit is susceptible to noise and signal attenuation while traveling on the interconnection. Integrated circuits using this flip-flop circuit will therefore be prone to malfunction. The amplitude is thus limited because the transistors connected in series, such as the transistors Q1 and Q3, Q2 and Q3, Q4 and Q6, and Q5 and Q6, exist in the course of the current path of the constant-current source I1 in the master latch CR41, for example.
When the difference between the power-supply voltages is made smaller, the suitable voltage level at the input terminals of the master latch CR41 and the slave latch CR42, or at the base of the transistor Q1, and the center of the logical amplitude of the input signal D do not meet. Hence, when the amplitudes and the levels of the amplitude centers of the input signal and the output signal are standardized as in an integrated circuit using a gate array, e.g., when the input/output signals must swing between -1.05 V and -1.55 V and it is difficult to change, it will be difficult to apply a flip-flop circuit using the series-gate ECL.
The above-described problem also applies to a latch circuit.
With a shift register circuit, a serial-parallel converting circuit and a parallel-serial converting circuit using the above-described flip-flop circuit, the problem is more serious because they have a larger number of flip-flop circuits.